Advanced Micro Devices, Inc. (NASDAQ:AMD) Wells Fargo 6th Annual 2022 TMT Summit November 30, 2022 11:00 AM ET
Company Participants
Mark Papermaster – CTO and Executive VP of Technology & Engineering
Conference Call Participants
Aaron Rakers – Wells Fargo
Aaron Rakers
Thank you so much, Mark. Thanks for having me here. So, I am extremely excited to have a discussion with you about architecture stuff and everything that’s going on at AMD over the past many years.
I’m going to start with a little stat though. When Mark joined October 24, 2011, I nailed debt. AMD’s enterprise value is $4 billion. Last night, the market closed, the stock was at $116 billion enterprise value. So I’m going to give you a ton of credit for that, Mark, phenomenal job.
And I think a lot of that is driven by the innovation engine, what you drive from the Company’s perspective. So maybe we’ll start the discussion with just a quick overview of how you think about AMD thinks about executing on the product road map, the vision.
We’ll talk about engineering organization and the size and how that’s expanded and maybe talk a little bit about the overlapping road map strategy. And wherever you want to take that because I think that’s really at the crux of what the AMD story has become here over the past many years.
Mark Papermaster
Well, thanks, Aaron. It is a big piece of the AMD story is our engineering execution. But it’s really about having a clear vision, a clear goal. And when Lisa and I were recruited into AMD, almost for me 11 years and just about 11 years ago for Lisa before she stepped into the CEO role, it was with a mantra to drive AMD back into sustained execution.
And both of our backgrounds, we had worked together back at IBM for many years. And we’re very knowledgeable in terms of what it takes to transform, for transforming leaders and technologists means you have a clear vision of where you’re going and you set out a clear methodology and process of how you achieve those goals and you line up the business objective.
So, it’s not actually just engineering. It has to be engineering and business and it has to be on the foundation of a culture. And that’s what’s really been absolutely critical for what the financial results, Aaron, that you summarized when you look back over that decade plus. And for us, there were some fundamentals.
AMD has to have a competitive CPU. It ties into everything that we do. We are — it’s the heritage of the Company. I mean that’s what led to the early success of AMD. And so a lot of the first focus was on writing the CPU road map. And that is where 10 years ago, we launched what was the architecture phase, what became the Zen x86 CPU family.
And it was set out to be not only a competitive processor, but a family of processors. And here we are just having released our fourth generation Zen first, middle of this year in client desktop and just recently with our first-generation EPYC servers.
So setting a clear goal to have leadership x86 compute capability at a base, but also with the vision of how do you build around that? How do you be more facile? And so we did from the outset architect. And that’s what a lot of people don’t realize is that they all look at Zen as being a catalyst that new competitive and leadership CPU architecture being a catalyst for AMD.
But on the technology side, equally was how we architected what we call the Infinity architecture, how all the pieces come together and how they, in fact, scale. And that was critical for AMD. AMD had acquired ATI and had huge pieces of IP around graphics and video acceleration, audio acceleration.
These elements that now you take for granted when you buy our laptops and all those elements just are so seamlessly woven together. I’m sure we’ll talk about it later. We’ve now done the same thing in the Data Center across our CPU and GPU and adaptive compute. But we laid the groundwork for that over a decade ago as we started the architecture of that Infinity architecture.
The thing about semiconductors is people don’t realize in software, you can make a change of direction. You can call the play and you can execute very, very quickly. In six months to a year, you can have a new direction set out. But in semiconductors, it’s a longer lead time. It’s four to five years when you set out a new direction.
And so, we did set out those new directions right away, but that culture of execution that had an immediate effect. So putting that into play allowed us to win game consoles, which were key in the early years, allowed us to revitalize our graphics road map and get into a culture of execution across the Company that when you look at it right now and you just look at — just take the last five years, it’s been a huge differentiator for us.
And when Lisa became CEO, she really galvanized the entire company around this culture of execution around a culture of listening to our customers so that we make sure that where that we’re targeting is where the customers need and on really excellence and quality. So it’s truly a fundamental underpinning of the performance you alluded to.
Question-and-Answer Session
Q – Aaron Rakers
So as a great overview, Mark. When we think about AMD and that road map execution, the Zen architecture and really going all in with a chiplet-based architecture versus the historical industry being more homogenous chip architecture. As you think about the road map, again, always probably thinking out the next four to five years, how far do you think that takes us? At what point do we have to think about another novel approach to an architecture besides just chiplets. And where does that stand on your thought process?
Mark Papermaster
Well, the way I’d suggest that we all think about it is innovation always finds its way around barriers. And you’ve all heard many times Moore’s Law is slowing down. Moore’s Law is dead. What does that mean? It’s not that there’s not going to be exciting new transistor technologies.
Actually, I can see exciting new transistor technology for the next — as far as you can really plot these things out, is about six to eight years, and it’s very, very clear to me the advances that we’re going to make to keep improving the transistor technology, but they’re more expensive. It used to be the old Moore’s Law, right?
You could double the density in every 18 to 24 months, but you’d stay at that same cost band. Well, that’s not the case anymore. So, we’re going to have innovations in transistor technology. We’re going to have more density. We’re going to have lower power, but it’s going to cost more. So, how you put solutions together has to change.
And we did see that coming, and that was part of the motivation of the Infinity architecture that we just spoke about because it allowed us to be very modular and how that we design each of the elements and that put us in a position to be able to leverage chiplets. Chiplets is really a way to just rethink about how the semiconductor industry is going forward.
There’s a lot of innovation yet to go because it’s going to be the new point of how solutions to put together. It used to be a motherboard and you put all these discrete elements in the motherboard. What will keep innovation going and we’ll keep, I’ll say, a Moore’s Law equivalent, meaning that you continue to really double that capability every 18 to 24 months is the innovation around how the solution is put together.
It will be heterogeneous. It won’t be homogeneous. So you’re going to have to use accelerators, GPU acceleration, specialized function, adaptive compute like we acquired with Xilinx, which closed in February this year. So those elements are going to have to come together and then how you integrate it is you’re going to see tremendous innovation on how those come together and it really will keep us on pace, and we actually have to because you can just look at the demands of computing, they haven’t slowed down one iota. In fact, they’re escalating rapidly with AI becoming more and more prevalent.
Aaron Rakers
Yes. And kind of as a side part of that comment, you’ve obviously had tremendous success in the hyperscale cloud customers. Are those cloud customers coming to AMD today and saying, look, we used to use x86 kind of general-purpose compute, but they’re increasingly coming and asking you to optimize compute platforms where there’s you mentioned heterogeneous compute that there’s more specific design architectural things that they’re doing hand-in-hand with AMD to kind of optimize their Data Center performance and power efficiency.
Mark Papermaster
It’s definitely the trend. When I remember, again, when I started just over a decade ago, I talked to the head of infrastructure of the largest hyperscale cloud offering at the time. And that leader told me, Mark, we’re going to be homogeneous, we’re not changing it. That’s how we get our efficiencies. We’re going to have just one family of CPUs across our Data Center.
But for the reasons I just said a moment ago, all the data centers have changed because you can’t keep pace with the computing demand. So if you have just one single x86 approach. So you need flavors, x86 is a dominant ISA architecture out there today, so it’s easiest to adopt. It doesn’t have to be x86. We can get back to that in a moment.
But we are already customizing when you look at our hyperscale installations we are already tailing to the kind of workload that they have. Is it image recognition? Is it search? Is it EDA, electronic design automation that needs a high frequency offering? So you look at our instances today on CPU alone and you’ll see many variations and more to come.
We’ll talk about Bergamo, our dense core that goes head-to-head with smaller arm cores where you just need throughput processing. Those are all tailored adaptations which we work with hyperscale because we listened because they told us what they needed to have cost-effective solutions and you’ll see more and more accelerators added into that mix. Microsoft announced that they have our instinct, our GPU acceleration now up and running in Azure for their training.
Aaron Rakers
Yes. That’s fantastic, and we’ll definitely — in the 18 minutes we’ve got left, but we’ll try to get to some of those. The biggest, I think, excitement recently has been this continual momentum you’ve had in the server market. You recently launched the Zen 4 architecture, Genoa, and maybe take us through kind of what are the key architectural things that are in Genoa that you’re excited about? And where I’m going to go with this ultimately is how are you expanding your ability to address the server market? Because I think that’s probably an underappreciated element of the AMD story just that ability to expand the breadth of the product portfolio.
Mark Papermaster
Yes, it’s a great question, Aaron. And let me take that almost as a two-part, if that’s okay, because — so let me first talk about Genoa. We couldn’t be more proud of general. Again, we try to really listen to our customers. They don’t want marketing. They just want total cost of ownership advantage.
And so with Genoa, it really delivers that and it delivers it in a timely way because when you look at the server fleets out there, people — there’s a major refresh cycle coming. And so if you look at IT operators, from hyperscale across enterprise, they’re looking to really improve their total cost reownership. Typically, you’re actually power limited on how you can achieve your total computing needs and you’re looking for economic growth.
What Genoa does is it leverages the fact that we took the CPU complex and moved it from 7-nanometer to 5-nanometer. So it’s on the cutting edge, TSMC 5-nanometer. Remember what I said earlier, the new transistors are still giving you more density and more performance per watt. So we combine 5-nanometer on the CPU with our design techniques, we partnered very closely from a design and technology standpoint with TSMC, and we improved 48% on the efficiency of computing.
So it’s a huge generational gain on performance per watt. And so that’s how we’re able to go from 64 cores in a single socket to 96 cores in a single socket. And so that’s element number one is really driving a very, very strong compute just on the raw core capability. It was our biggest generational gain of that kind of efficiency.
But our customers also need balanced computing. That’s only as good as if you feed it. You have the I/O memory. So we jumped to PCIe Gen 5. We doubled the I/O bandwidth coming in and out, and we went from DDR4 to DDR5, the newest memory which runs much faster. So and we increased from eight lanes going out to that memory to 12 lanes going out that memory.
So a significant memory bandwidth and I/O bandwidth, that’s how we’re able to jump to 96 scores, have that energy efficiency, leveraging TSMC. We kept I/O memory on the older more economic node, so it kept the costs in control. And that’s again our chiplet architecture. So we have different technology nodes all in a single solution. And the result is just a massive TCO benefit for the customers.
And part two of your question is exactly we’re expanding our TAM. And so when you have that kind of offering, what we’re able to do with that kind of performance is, one, we offer Genoa to sit right on top of our third-generation EPYC, Milan because Milan is still a leadership processor in the server market.
And so one, we have the — from top to bottom of stack has incredible coverage now with the kind of granularity that our customers need to really cover hyperscale through enterprise, and we are adding in first half of this year, what we call Bergamo, which will be with our Zen 4c, we increased staffing to our CPU team, and we added a version of Zen 4. It’s still Zen 4. It runs a code just like Genoa, but it’s half the size.
And that competes head-to-head with Graviton and ARM-based solutions where you don’t need the peak frequency. You’re running workloads like Java workloads, throughput workloads that don’t have to run peak frequency, but you need a lot of cores. So we’re adding that in first half of ’23. And then later in 2023, we’re adding the Sienna which is a variant targeted to telecom space. So we’re really, really excited about our TAM growth in server.
Aaron Rakers
Yes. So one of the questions I get is as you’ve clearly executed on gaining share in the server market, taking that performance leadership and continuing to build on that. The question I often get is how does pricing factor in to the competitive landscape? And there’s always a concern that hey, a competitor is going to get more aggressive, maybe ARM shows up more. How do you see the pricing envelope factor into your strategy from a server side perspective?
Mark Papermaster
It’s a great question, and that’s really one of the driving forces in the TAM expansion. So what you’re seeing is the market is growing so dramatically, it’s trying new competitors in. And everyone is looking for their niche, and that’s where you’re going to provide — if you can provide a niche where you’re really tailoring to a specific workload then you can drop out circuitry not needed for other workloads and have a more economic solution.
So it really — Aaron, was a driving force in us expanding the offerings that we have. One, what I talked about earlier, positioning Genoa such strong performance on top of Milan. So that gives us flexibility of price over that broad range of offerings that we have from Genoa from fourth gen EPYC inclusive of third gen EPYC.
But also, again, with Bergamo coming with that dense core in first half of 2023 is also intended to give us that TCO advantage. People don’t buy on just pure price, they’re looking at the total cost of ownership, and they’re looking at the total cost of ownership for their workload. So, the way we’re attacking price is making sure that we have the configurations that are tailored to the workloads our customers are running and are priced to give them significant total cost of ownership advantage.
Aaron Rakers
With Genoa, Genoa X or Genoa C, Bergamo, Siena, is there other whitespace that you see in the data center area for you guys to continue to expand the portfolio?
Mark Papermaster
Well, you mentioned Genoa X. And I didn’t mention that in the variance and I’ll add that now. That’s a version where we stack cash right on top of the CPU and that really is tailored to make high-performance workloads like EDA or database workloads, even more TCO effective.
So yes, with — we we’ve covered the, I’ll say, the prime markets. When you start looking beyond the variance that we have now, you start getting to more, I’ll say, corner cases of the market. And again, we will listen to our customers. Work closes change over time and particularly now you’re seeing, again, AI almost every kind of application.
So we’re building AI into each one of those variants. And that’s, to us, is the white space that we’re now covering. We started it with fourth gen EPYC with Genoa, and you’ll see more and more AI capabilities in our road map as we go forward.
Aaron Rakers
That’s perfect. So I’m going to maybe shift outside just the server side of the world. But one of the other things that AMD has done is you have a GPU strategy with Instinct. You mentioned Microsoft up and running with Instinct instances. You’ve got an FPGA strategy with the Xilinx asset. They had some Data Center strategy there. You have Pensando, which you bought. I think it was earlier this year, for data — DPUs. Where do you see — when do we start to see maybe some of these other adjacent data center pieces of the portfolio? How are you thinking about those materializing?
Mark Papermaster
The two acquisitions, Aaron, that you mentioned, with Xilinx and Pensando were fundamental. I don’t think people quite realize how important those acquisitions were in terms of rounding out the AMD portfolio. So when you think about what Xilinx brought to bear, it is adaptive compute, which is inclusive of FPGAs but it is also where even more tailored solutions are needed.
So it has embedded ARM cores. Higher performance ARM cores has embedded accelerators along with that adaptive compute along with networking capability it brings to bear, a very strong embedded track record with telecommunications, defense, a broad range of applications and a growing footprint in the Data Center.
And with Pensando, we have a programmable smart neck that’s absolutely a leadership play. It’s being adopted in hyperscale, and it has 144 P4 engines. P4 is a programming language now becoming the de facto standard to allow micro services to come into the data center.
And the Pensando offerings now in its second generation is an absolute leader in flexibility in being able to tailor these solutions whether you need software-defined storage, whether you need a firewall, a deep packet inspection capability, whether you need optimization of your of offloading — offloading capabilities from the CPU. All of these are examples of where the SmartNIC can be deployed.
And so these additions are really enabling us to deepen our footprint with our customers. And honestly, when you look at the trend, you’re seeing the need for performance such that the CPUs, the accelerators and the connectivity have to move in tandem to provide the kind of performance that’s needed going forward.
Aaron Rakers
Yes. We touched on it earlier in the architectural overview, but I want to double-click on Infinity architecture a little bit and maybe understand the evolution of that because it seems to be a key building block of the strategy. And and probably remains the case going for. How do we think about what you see in Infinity architecture as far as the evolution going forward? Does it ever become off-chip interconnect? Is there more to be set around just Infinity in general?
Mark Papermaster
Yes. When you hear that term from AMD, you need to think about it as it’s AMD’s scalability architecture. It’s what allows us to go from a one-socket CPU to a two-socket CPU and scale almost linearly. Why? Because at Infinity architecture connecting one socket to two socket is the same guts, the same technology guts that’s in a single-chip implementation of our CPU.
So as we connect on a single die and then we can act that single die to another die, it’s the same architecture, seamlessly allowing you to scale. Then we extended that to GPU when you connect the GPU to the CPU. It’s that same Infinity architecture, the same fundamental approach, allowing you to have very, very high bandwidth, high connectivity and low latency to allow you to scale CPU to GPU. We do that, of course, in our client products.
But with what we announced at we’ve rolled out with our next-generation instinct that we’re already have back in the labs, our MI 300. It is a true Data Center APU. It’s a CPU and a GPU acceleration which is leveraging the Infinity architecture to share the same memory fully coherently. It’s all sharing a high-bandwidth memory.
And so it goes beyond that. So it’s not — now when you think about what I commented on earlier with chiplet, the Infinity architecture going forward will encompass it to chiplet interconnect. We do that already today with our chiplets. We have over 40 chiplets in production today, but we are a founding member of UCIe. UCIe is the new standard. It can take a few years. But that standard has tremendous momentum, and it will create an ecosystem of how chiplets can be put together.
And that will allow us to even further help hyperscalers tailor their solutions when you can put a hyperscaler accelerator together with our chips and we have a semi-custom division, we call S3, that’s already stood up and working with our end customers to enable that kind of customization. So Infinity architecture was architected to be tremendously flexible and is absolutely key for us to hit the industry trends going forward.
Aaron Rakers
So this might be not related — I’m not quite sure, but I’ve written a lot — our team has written a lot about CXL as an interconnect and connecting big pools of memory and other peripherals. Does CXL competitive with Infinity architecture? Is it a complement? I’m just curious how you see the parallels between what seems to be more and more kind of interconnect.
Mark Papermaster
Yes. So those are not to move CXL’s Connect XpressLink, and it’s a standard that is — will actually be used as well as part of the whole chiplet interconnect. But it allowed in a standard way for us to avoid bus wars in the industry of how we all attach acceleration or memory extensions on to our compute complexes.
And it’s a great story of collaboration by the way, because AMD led the way with Xilinx with ARM, with others, and we’re going on a standard that was called CCIX and Intel was going to another direction. And all of the parties came together and Intel had started the proposal of CXL.
And we looked at it and said, Look, if we can make this a level playing field, we can avoid bus wars in the industry, different standards that just compete each other and compete against each other and prohibit an ecosystem coming from together. And so we did bring that consortium together very successfully.
And in general, we do have support for CXL. We call it 1.1 plus. That’s the standard, the first generation and why we call it plus is, we added the support for what’s called Type 3 memory pooling. So on fourth gen EPYC, our Genoa system today, you can extend the memory and add memory, by the way, you could — as I told you, Genoa is a DDR5, the latest memory. But let’s say you want additional memory that’s less expensive.
You want to run DDR4. You can use CXL to have DDR4 to extend your memory, and you can actually pull the memory across different nodes using a CXL switch, and it’s just the start. You’re going to see CXL over multiple generations create a whole ecosystem of accelerators and solutions by the time we get to Generation 3 of CXL. You’re going to see it support even clustering solutions across the standard.
Aaron Rakers
So Mark, we’ve got two minutes left, and this is probably a longer discussion than just two minutes, but I’m just going to ask you because I get the question a lot. ARM in the Data Center, how do you see ARM architecture evolving competitively? And I know you mentioned Bergamo as a competitor.
Mark Papermaster
Yes. So it’s really people get confused on this point. They think it’s an ARM versus x86 versus Risk 5, it’s really all about the solution that you put together. The reason we had actually, as some of you recall, we had our road map when you go back eight, nine years ago, had both ARM and x86 and a road map and we defeatured the arm in our CPU road map because the ecosystem still had too far to go.
We could have made that — we had a design approach that was going to make the custom arm design for AMD equally performant to the x86, but the ecosystem wasn’t there. So we kept our focus on x86, and we said, let’s watch the space in ARM. ARM is now developing more of a robust ecosystem.
And we certainly have a very straightforward strategy. Keep our x86 performance going as such that it’s a leadership capability. So if you want to tap the ecosystem that’s most dominant out there, we want to have just absolute leadership capability in TCO for the comments I made earlier.
But if someone has reasons that they want ARM, we have our custom group, that S3 group I described earlier, and we’re happy to work with them to implement in our base solution. We’re not we’re not married to an ISA. We’re married to getting our customers the absolute best solution and delivering incredible value to them.
Aaron Rakers
And again, important to note Versal within the Xilinx asset had ARM cores, it’s very — it’s almost like a Swiss army knife of compute with multiple different facets of…
Mark Papermaster
Versal is ARM-based, we’re not changing that. Pensando, SmartNIC is ARM based, we’re not changing that. Those are great examples because those are tailor-made applications that don’t need that whole ecosystem. When you use a Xilinx device, when you use a SmartNIC device, you don’t need that ecosystem of applications because it’s a point application. It’s a tailored application.
Aaron Rakers
Mark, thank you so much for joining us. That’s great. Great overview. Thank you.
Mark Papermaster
Thanks for having me, Aaron. I appreciate it.
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